This invention relates in general to self-protected semiconductor controlled rectifier devices and more particularly to self-protected semiconductor controlled rectifier devices provided with means to prevent voltage breakdown thereto in excess of current leakage when in operation under high temperatures or in excess of withstand value of voltage increasing rate dV/dt.
As the technique to prevent voltage breakdown in semiconductor controlled rectifier devices thereto in excess of current leakage when operating the self-protected semiconductor controlled rectifier device under high temperatures or in excess of withstand value of voltage increasing rate dV/dt, the so called short emitter structure is witherto used.
The short emitter structure is understood to be a structure wherein an emitter junction at the cathode side is short-circuited at some places to the cathode so that when in off state a voltage having high withstand voltage increasing rate dV/dt is applied between the anode and cathode of the semiconductor controlled rectifier device the generated displacement current is by-passed through the above mentioned short-circuited places thus suppressing the injection of carriers from the emitter junction to the cathode and consequently the turning-on due to the withstand value of voltage increasing rate dV/dt is protected.
Further a method of increasing the short-circuit density in the short emitter has been employed to increase the withstand value of voltage increasing rate dV/dt, but in case when the short-circuit density is too large the semiconductor controlled rectifier device loses its conduction characteristics. Therefore, there is a limit imposed on the increase of the withstand value of voltage increasing rate dV/dt in semiconductor controlled rectifier devices. For example, for common power thyristors with specifications of 2500-4000 volts and 1000 ampere the maximum value of the above mentioned dV/dt is in the order of 1500-2000 V/.mu.s.
There has been proposed a method for improving an above mentioned limit, which relates to incorporation in a semiconductor controlled rectifier device comprising a main thyristor section consisting of a main thyristor region having four continuous layers of alternate and different conductivities of PNPN with a couple of main electrodes connected in ohmic contact with the two outside layers of the main thyristor region, and a gate electrode connected to one of the layers. The incorporation is such that a pilot thyristor section and an auxiliary pilot thyristor section with higher gate sensitivity in comparison with that of the main thyristor section are incorporated in the semiconductor controlled rectifier device. Such a construction is disclosed U.S. Pat. No. 4,012,761 "SELF PROTECTED SEMICONDUCTOR DEVICE".
In general, however, the least gate current I.sub.gt necessary to turn on the semiconductor controlled rectifier device is defined as of hereunder. I.sub.gt should be selected in such way as to satisfy the relation I.sub.gt1 &lt;I.sub.gt &lt;I.sub.gt2, where I.sub.gt1 is the value of the gate current which turns on by mistake the semiconductor controlled rectifier device when in operation under high temperatures, and I.sub.gt2 is the value of the current imposed by the power restrictions on the gate circuit. As a result, the value of the resistance of the layer through which the gate current flows, should also be selected such as to satisfy the relation I.sub.gt1 &lt;I.sub.gt &lt;I.sub.gt2.
The structure presented in U.S. Pat. No. 4,012,761 is described hereinbelow. The pilot or auxiliary thyristors have a greater turn-on sensitivity than the main emitter region. This means that when main thyristor section, pilot thyristor section and auxiliary pilot thyristor section have withstand values of voltage increasing rate dV/dt respectively of .vertline.dV/dt.vertline.main, .vertline.dV/dt.vertline.pil and .vertline.dV/dt.vertline.aux, there is required that the condition of .vertline.dV/dt.vertline.main&gt;.vertline.dV/dt.vertline.pil, .vertline.dV/dt.vertline.aux should be satisfied. However, there is nothing said about the mutal relation between .vertline.dV/dt.vertline.pil and .vertline.dV/dt.vertline.aux. In order to fulfill the condition of .vertline.dV/dt.vertline.main&gt;.vertline.dV/dt.vertline.pil, the previously mentioned resistance of the layer wherein the gate current flows should be selected such as to satisfy this condition. In U.S. Pat. No. 4,012,761, as a result, the reistance of the layer wherein the gate current flows should satisfy both conditions of I.sub.gt1 &lt;I.sub.gt &lt;I.sub.gt2 and .vertline.dV/dt.vertline.max&gt;.vertline.dV/dt.vertline.pil at the same time. Consequently, the choice of the resistance of the layer wherein the gate current flows, is bound to a narrow range, which poses a disadvantage.
In case of both of the hereinabove mentioned conditions being fulfilled for the selected resistance of the layer through which the gate current flows, U.S. Pat. No. 4,012,761 still possesses the hereinbelow stated weak points. Namely, in the mentioned U.S. Pat. No. 4,012,716, in the edge between the second and third layer there is provided first negatively beveled region which reduces the electric field intensity thereat and increases the ultimate breakdown voltage of the semiconductor controlled rectifier device. The junction layer between the second and third layer of the above mentioned beveled region shows a trend to become inefficient. The leakage current in the surface layer of the junction increases therefore and the auxiliary pilot thyristor exhibits a weak point turning-on at a voltage lower than the operational one.